Repetitions:
* 0x17c07c1f (looks like padding?)
* 0x1b80001f

* 0xf0000000: might be return? often before "padding"

* PCM_HANDSHAKE_SEND1 0xbeefbeef
* PCM_MCDI_HANDSHAKE_SYNC 0xbeefbeef
* PCM_MCDI_HANDSHAKE_ACK 0xdeaddead
* PCM_MCDI_UPDATE_INFORM 0xabcdabcd
* PCM_MCDI_CKECK_DONE 0x12345678

SPM_PCM_REG5_DATA:
* 0xaa55aa55 PCM_MCDI_OFFLOADED
* 0x0 PCM_MCDI_ALL_CORE_AWAKE

SPM_PCM_REG6_DATA (CPU read):
* PCM_MCDI_HANDSHAKE_ACK
* PCM_MCDI_CKECK_DONE

SPM_PCM_REG_DATA_INI (CPU write):
* PCM_MCDI_HANDSHAKE_SYNC
* PCM_MCDI_UPDATE_INFORM

reg6 values prefixed with 0x1980001f
reg5 0x1940001f

register write procedure:
	mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM);
	mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
	mmio_write_32(SPM_PCM_PWR_IO_EN, 0);

writes PCM_MCDI_UPDATE_INFORM to R6

register read procedure:
mmio_read_32(SPM_PCM_REG5_DATA)

PCM-side register write with next word as immediate 32 bit value:
0001 1000 xxxx 0000 0000 0000 0001 1111
           ^
           +--- register (0-15)

CPU wake up event steps:
* CPU sets r6 = 0xbeefbeef (PCM_MCDI_HANDSHAKE_SYNC)
* PCM expects r6 = 0xdeadbeef (PCM_MCDI_HANDSHAKE_SYNC)
0x69200006, 0xbeefbeef

* PCM set r6 (0x98) = 0xdeaddead (PCM_MCDI_HANDSHAKE_ACK)
0x1980001f, 0xdeaddead

* CPU sets r6 = 0xabcdabcd (PCM_MCDI_UPDATE_INFORM)
* PCM expects r6 = 0xabcdabcd (PCM_MCDI_UPDATE_INFORM)
0x69200006, 0xabcdabcd

* PCM sets r6 (0x98) = 0x12345678 (PCM_MCDI_CKECK_DONE)
0x1980001f, 0x12345678

* CPU expects r6 == 0x12345678 (PCM_MCDI_CKECK_DONE)
* CPU sets r6 (0x98) = 0

suspend-specific:
* PCM_PWRIO_EN_R0 | PCM_PWRIO_EN_R7
* then the firmware sets a sequence to those values
* each bit of the register is likely wired to I/O that does something PM-related